1. Field of the Invention
The present invention relates in general to integrated circuit testers and in particular to an integrated circuit tester capable of testing asynchronous integrated circuit devices.
2. Description of Related Art
A typical integrated circuit (IC) tester includes a separate channel for each terminal of an IC device under test (DUT). The tester organizes an IC test into a succession of test cycles, and during each test cycle, each channel may either send a test signal to a DUT terminal or monitor a DUT output signal at the terminal to determine if the DUT is behaving as expected. The actions each channel carries out during each test cycle are controlled by data (a "test vector") provided to each channel at the start of each test cycle. Each vector may indicate not only an action the channel is to carry out during a test cycle, but may also indicate a particular time during the test cycle the channel is to carry out the action. Thus the sequence of vectors provided to each channel during a test totally defines the channel's behavior during the test. A vector telling a channel to sample a DUT output signal at some time during a test cycle may also include "EXPECT" data indicating an expected state of the DUT output signal. The tester compares the EXPECT data to the sample DUT output to determine when the DUT has failed. Some testers allow a channel detecting a DUT failure to send an output FAIL signal to a central controller. The central controller can then signal the other channels to halt the test and to prepare to test another DUT.
In some testers a central controller provides vectors to each channel before the start of each test cycle. In other testers each channel includes a memory for storing a set of test vectors and a sequencer for sequentially addressing the memory so that it reads out a test vector before the start of each test cycle. In still other testers, a vector-generating algorithm is stored in each channel's memory and each channel includes an instruction processor for executing the algorithm to produce a vector for each test cycle.
Integrated circuit testers are synchronous devices. Each channel times state changes in the test signal it sends to the DUT and times its sampling of a input signal from the DUT with reference to a common master clock signal. The sequence of vectors supplied to a channel completely defines the sequence of actions the channel takes and the times at which those actions are to occur. Thus testers are "time driven" in the sense that the actions the tester's channels carry out depend only on the passage of time and not on occurrence of any particular events. Since the sequence and timing of test actions a tester performs must follow a predetermined time-driven script, an integrated circuit tester is not well adapted for testing DUT's producing output signals that change state at unpredictable times. For example if a DUT is a synchronous device having its own internal clock, it must either communicate asynchronously with the outside world, or must provide its internal clock signal to any external device it communicates with so that the external device can synchronize its activities to those of the DUT. Since conventional IC testers operate from their own master clocks, and since the DUT's clock is not synchronized to the tester's master clock, a conventional tester can't predict precisely when the DUT is going to carry out some action. For example, the tester can't precisely tell when the DUT's output data is valid. Since the vector sequence programming a conventional tester can only tell the tester to sample the DUT's output signals at certain times with respect to the tester's master clock, a conventional IC tester can't test such a DUT as it is used or simulated.
What is needed is an IC tester that can fully test a DUT that is not synchronized to the tester's master clock. Such a tester should be able to communicate with the DUT asynchronously and should be "event driven" in the sense that it should be able to take actions initiated by state changes in the DUT output signals in addition to actions initiated merely by the passage of time relative to its own master clock signal.